1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating an electrostatic discharge (ESD) protection circuit for a semiconductor device.
2. Description of Related Art
In the fabrication of an integrated circuit (IC) device, such as dynamic random access memory (DRAM) or statistic random access memory (SRAM), ESD is one of the main factors causing IC damage. For example, when one walks on a carpet with semiconductor wafers, if relative humidity (RH) is high, an electrostatic voltage of about a few hundred volts may exist on one's body and wafers. If the RH is very low, the electrostatic voltage may be even as high as about a few thousand volts. If a conductive object occasionally contacts the wafers, a strong ESD could occur and damage the ICs on the wafers. ESD is an especially serious problem for fabrication of a complementary metal-oxide semiconductor (CMOS) device.
In order to protect wafers from ESD damage, many methods to solve the ESD problem have been proposed. The most common conventional method is to make an ESD protection circuit between input/output (I/O) pads and internal circuits so that the ESD does not damage the ICs fabricated on the wafers. Currently, the ESD problem is one of main factors causing damage to the IC device at deep sub-micron level. It is very desired to have an ESD protection circuit, which can effectively protect IC devices from ESD damage.
FIGS. 1A-1D are cross-sectional views of a portion of a substrate, schematically illustrating a conventional fabricating process to form an ESD protection circuit. In FIG. 1A, a semiconductor substrate 100 typically includes an internal circuit region 120 and an ESD circuit region 220. The internal circuit region 120 includes a normal circuit, such as a metal-oxide semiconductor (MOS) transistor 130 with a lightly doped drain (LDD) structure. Each gate structure also includes a spacer on each sidewall of the gate structures. The ESD protection circuit region 220 includes a protection circuit, which, for example, includes a MOS transistor 230 with a LDD structure. A self-aligned silicide (Salicide) layer is also formed on gate structures and source/drain regions of the MOS transistors 130 and 230. The source/drain region is formed in the substrate 100 at each side of the gate. For example for the MOS transistor 230, a Salicide layer 234 covers the gate structure, a Salicide layer 236 covers the source/drain region, and a spacer 238 is formed at each sidewall of the gate structure.
In FIG. 1B, a patterned photoresist layer 232 is formed over the substrate 100, in which the photoresist layer 232 covers the internal circuit region 120, the Salicide layer 230, and a portion of the Salicide layer 236 of the MOS transistor 230 at each side of the gate structure. So, a portion of the Salicide layer 236 on the source/drain region and the spacer 238 of the MOS transistor 230 are exposed. Using the photoresist layer 232 as a mask, the spacer 238 and the exposed portion of the Salicide layer 236 at the ESD protection circuit region 220 are removed by etching. A remaining portion of the Salicide layer 236 becomes a Salicide layer 236a. In this manner, during etching the Salicide layer 236 on the source/drain region, a substrate surface of the substrate 100 at the ESD protection circuit region 220 may be damaged, resulting in a poor performance of the ESD protection circuit.
In FIG. 1C, an ion implantation process with a dopant type the same as a dopant type for the source/drain region is performed so as to merge the LDD structure, which is under the spacer 238 in FIG. 1A, with the source/drain region.
In FIG. 1D, the photoresist layer 232 of FIG. 1C is removed. A dielectric layer is formed over the substrate 100. A contact opening 150 is formed in the dielectric layer at the internal circuit region 120, and a contact opening 250 is formed in the dielectric layer at the ESD protection circuit region 220 so as to expose the Salicide layer 236a on the source/drain region of the MOS transistor 230. The rest part of the fabrication process to accomplished the ESD protection circuit is well known by the one skilled in the art and is not further described.
In the conventional method as described above, it includes two photoresist layers for patterning the Salicide layer and the ion implantation process. Fabrication cost is high. Moreover, when the Salicide layer on the source/drain region is patterned, the substrate surface at the ESD protection region may be damaged, resulting in a poor performance of the ESD protection circuit.